Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders
arXiv:1907.10826
Abstract
In this technical note, we provide a comparison of the design metrics of various quasi-delay-insensitive (QDI) asynchronous adders, where the adders correspond to diverse architectures. QDI adders are robust, and the objective of this technical note is to point to those QDI adders which are suitable for low power/energy and less area. This information could be valuable for a resource-constrained low power VLSI design scenario. Non-QDI adders are excluded from the comparison since they are not robust although they may have optimized design metrics. All the QDI adders were realized using a 32/28nm CMOS process.
arXiv commentarXiv admin note: substantial text overlap with arXiv:1903.09433
References in corpus (5)
- An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder
- Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding
- Critique of "Asynchronous Logic Implementation Based on Factorized DIMS"
- Asynchronous Ripple Carry Adder based on Area Optimized Early Output Dual-Bit Full Adder
- Performance Comparison of some Synchronous Adders