Surface structures of tellurium on Si(111)-(7x7) studied by low-energy electron diffraction and scanning tunneling microscopy

Abstract

The Te-covered Si(111) surface has received recent interest as a template for the epitaxy of van der Waals (vdW) materials, e.g. Bi${}_2$Te${}_3$. Here, we report the formation of a Te buffer layer on Si(111)$-$(7$\times$7) by low-energy electron diffraction (LEED) and scanning tunneling microscopy (STM). While deposition of several monolayer (ML) of Te on the Si(111)$-$(7$\times$7) surface at room temperature results in an amorphous Te layer, increasing the substrate temperature to $770\mathrm{K}$ results in a weak (7$\times$7) electron diffraction pattern. Scanning tunneling microscopy of this surface shows remaining corner holes from the Si(111)$-$(7$\times$7) surface reconstruction and clusters in the faulted and unfaulted halves of the (7$\times$7) unit cells. Increasing the substrate temperature further to $920\mathrm{K}$ leads to a Te/Si(111)$-(2\sqrt{3}\times 2\sqrt{3})R30^{\circ }$ surface reconstruction. We find that this surface configuration has an atomically flat structure with threefold symmetry.

References in corpus (5)

• Topological Surface States Protected From Backscattering by Chiral Spin Texture
• Electrical resistance of individual defects at a topological insulator surface
• Surface and Step Conductivities on Si(111) Surfaces
• Scanning tunneling potentiometry implemented into a multi-tip setup by software
• Four-point probe measurements using current probes with voltage feedback to measure electric potentials

Cited by in corpus (1)

• Parasitic conduction channels in topological insulator thin films