Comments on "Dual-rail asynchronous logic multi-level implementation"
arXiv:1802.00004 · doi:10.1016/j.vlsi.2015.08.001
Abstract
In this research communication, we comment on "Dual-rail asynchronous logic multi-level implementation" [Integration, the VLSI Journal 47 (2014) 148-159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.