40.2k citations
Counting papers with at most 25 authors, so collaboration author lists do not stand in for the people here.
- National Institute of Chemical Physics and BiophysicsEE28 papers
- University of TartuEE15 papers
- Istituto Nazionale di Fisica Nucleare, Sezione di PadovaIT10 papers
- University of OxfordGB10 papers
- University of PaduaIT10 papers
- University of CambridgeGB9 papers
- Aalto UniversityFI8 papers
- Centre National de la Recherche ScientifiqueFR8 papers
- European Organization for Nuclear ResearchCH8 papers
- University of HelsinkiFI8 papers
- King's College LondonGB7 papers
- Reykjavík UniversityIS6 papers
14 papers · 1 filter
FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference
Natalia Cherezova, Artur Jutman, Maksim Jenihhin
The emergence of Deep Neural Networks (DNNs) in mission- and safety-critical applications brings their reliability to the front. High performance demands of DNNs require the use of…
A Novel Fault-Tolerant Logic Style with Self-Checking Capability
Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani +1
We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functi…
HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study
Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze +1
With the current increase in the data produced by the Large Hadron Collider (LHC) at CERN, it becomes important to process this data in a corresponding manner. To begin with, to ef…
Systematic Unsupervised Recycled Field-Programmable Gate Array Detection
Yuya Isaka, Michihiro Shintani, Foisal Ahmed +1
With the expansion of the semiconductor supply chain, the use of recycled field-programmable gate arrays (FPGAs) has become a serious concern. Several methods for detecting recycle…
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2
Rapidly shrinking technology node and voltage scaling increase the susceptibility of Soft Errors in digital circuits. Soft Errors are radiation-induced effects while the radiation…
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2
As an alternative to traditional fault injection-based methodologies and to explore the applicability of modern machine learning algorithms in the field of reliability engineering,…
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors
Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux +2
The paper is proposing a methodology for modeling a gate-level netlist using a Graph Convolutional Network (GCN). The model predicts the overall functional de-rating factors of seq…
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL
Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar +1
The advanced complex electronic systems increasingly demand safer and more secure hardware parts. Correspondingly, fault injection became a major verification milestone for both sa…
New categories of Safe Faults in a processor-based Embedded System
C. C. Gursoy, M. Jenihhin, A. S. Oyeniran +4
The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its…
Efficient Fault Injection based on Dynamic HDL Slicing Technique
Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik +1
This work proposes a fault injection methodology where Hardware Description Language (HDL) code slicing is exploited to prune fault injection locations, thus enabling more efficien…
Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing
Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik +1
Along with the complexity of electronic systems for safety-critical applications, the cost of safety mechanisms evaluation by fault injection simulation is rapidly going up. To red…
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin +2
Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of th…
Towards Multidimensional Verification: Where Functional Meets Non-Functional
Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri +1
Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems…
Mixed-level identification of fault redundancy in microprocessors
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin +2
A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the instruction set, and is spec…