most citedRedundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits

4 citations

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2 papers

cs.AR2017

Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits

P Balasubramanian, R T Naayagi

In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the…

cs.AR2017★ 4 cited

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits

P Balasubramanian, R T Naayagi

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit…