2 papers
cs.CR2025
Enter, Exit, Page Fault, Leak: Testing Isolation Boundaries for Microarchitectural Leaks
Oleksii Oleksenko, Flavien Solt, Cédric Fournet +3
CPUs provide isolation mechanisms like virtualization and privilege levels to protect software. Yet these focus on architectural isolation while typically overlooking microarchitec…
cs.CR2024
Dorami: Privilege Separating Security Monitor on RISC-V TEEs
Mark Kuhne, Stavros Volos, Shweta Shinde
TEE implementations on RISC-V offer an enclave abstraction by introducing a trusted component called the security monitor (SM). The SM performs critical tasks such as isolating enc…