3 citations · 7 across the 3 of their papers we have counts for
3 papers
Specification and Reactive Synthesis of Robust Controllers
Paritosh K. Pandya, Amol Wakankar
This paper investigates the synthesis of robust controllers from logical specification of regular properties given in an interval temporal logic QDDC. Our specification encompasses…
DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis
Amol Wakankar, Paritosh K. Pandya, Raj Mohan Matteplackel
DCSYNTH is a tool for the synthesis of controllers from safety and bounded liveness requirements given in interval temporal logic QDDC. It investigates the role of soft requirement…
Formalizing Timing Diagram Requirements in Discrete Duration Calulus
Raj Mohan Matteplackel, Paritosh K. Pandya, Amol Wakankar
Several temporal logics have been proposed to formalise timing diagram requirements over hardware and embedded controllers. These include LTL, discrete time MTL and the recent indu…