113 citations · 290 across the 25 of their papers we have counts for
27 papers
A Survey of Techniques for Optimizing Transformer Inference
Krishna Teja Chitty-Venkata, Sparsh Mittal, Murali Emani +2
Recent years have seen a phenomenal rise in performance and applications of transformer neural networks. The family of transformer networks, including Bidirectional Encoder Represe…
TPFNet: A Novel Text In-painting Transformer for Text Removal
Onkar Susladkar, Dhruv Makwana, Gayatri Deshmukh +3
Text erasure from an image is helpful for various tasks such as image editing and privacy preservation. In this paper, we present TPFNet, a novel one-stage (end-toend) network for…
ACLNet: An Attention and Clustering-based Cloud Segmentation Network
Dhruv Makwana, Subhrajit Nag, Onkar Susladkar +4
We propose a novel deep learning model named ACLNet, for cloud segmentation from ground images. ACLNet uses both deep neural network and machine learning (ML) algorithm to extract…
WaferSegClassNet -- A Light-weight Network for Classification and Segmentation of Semiconductor Wafer Defects
Subhrajit Nag, Dhruv Makwana, Sai Chandra Teja R +2
As the integration density and design intricacy of semiconductor wafers increase, the magnitude and complexity of defects in them are also on the rise. Since the manual inspection…
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads
Jens Domke, Emil Vatai, Balazs Gerofi +9
Over the last three decades, innovations in the memory subsystem were primarily targeted at overcoming the data movement bottleneck. In this paper, we focus on a specific market tr…
Modeling Data Reuse in Deep Neural Networks by Taking Data-Types into Cognizance
Nandan Kumar Jha, Sparsh Mittal
In recent years, researchers have focused on reducing the model size and number of computations (measured as "multiply-accumulate" or MAC operations) of DNNs. The energy consumptio…
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs
Nandan Kumar Jha, Sparsh Mittal, Binod Kumar +1
The remarkable predictive performance of deep neural networks (DNNs) has led to their adoption in service domains of unprecedented scale and scope. However, the widespread adoption…
On the Demystification of Knowledge Distillation: A Residual Network Perspective
Nandan Kumar Jha, Rajat Saini, Sparsh Mittal
Knowledge distillation (KD) is generally considered as a technique for performing model compression and learned-label smoothing. However, in this paper, we study and investigate th…
DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator
Nandan Kumar Jha, Shreyas Ravishankar, Sparsh Mittal +3
The number of processing elements (PEs) in a fixed-sized systolic accelerator is well matched for large and compute-bound DNNs; whereas, memory-bound DNNs suffer from PE underutili…
ULSAM: Ultra-Lightweight Subspace Attention Module for Compact Convolutional Neural Networks
Rajat Saini, Nandan Kumar Jha, Bedanta Das +2
The capability of the self-attention mechanism to model the long-range dependencies has catapulted its deployment in vision models. Unlike convolution operators, self-attention off…
E2GC: Energy-efficient Group Convolution in Deep Neural Networks
Nandan Kumar Jha, Rajat Saini, Subhrajit Nag +1
The number of groups () in group convolution (GConv) is selected to boost the predictive performance of deep neural networks (DNNs) in a compute and parameter efficient manner.…
The Ramifications of Making Deep Neural Networks Compact
Nandan Kumar Jha, Sparsh Mittal, Govardhan Mattela
The recent trend in deep neural networks (DNNs) research is to make the networks more compact. The motivation behind designing compact DNNs is to improve energy efficiency since by…
A Survey of Techniques for Dynamic Branch Prediction
Sparsh Mittal
Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions execu…
A Survey of Techniques for Improving Security of GPUs
Sparsh Mittal, S. B. Abhinaya, Manish Reddy +1
Graphics processing unit (GPU), although a powerful performance-booster, also has many security vulnerabilities. Due to these, the GPU can act as a safe-haven for stealthy malware…
Mitigating Read-disturbance Errors in STT-RAM Caches by Using Data Compression
Sparsh Mittal
Due to its high density and close-to-SRAM read latency, spin transfer torque RAM (STT-RAM) is considered one of the most-promising emerging memory technologies for designing large…
Power Management Techniques for Data Centers: A Survey
Sparsh Mittal
With growing use of internet and exponential growth in amount of data to be stored and processed (known as 'big data'), the size of data centers has greatly increased. This, howeve…
A Survey of Methods For Analyzing and Improving GPU Energy Efficiency
Sparsh Mittal, Jeffrey S. Vetter
Recent years have witnessed a phenomenal growth in the computational capabilities and applications of GPUs. However, this trend has also led to dramatic increase in their power con…
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Sparsh Mittal
Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the popula…
A Study of Successive Over-relaxation Method Parallelization Over Modern HPC Languages
Sparsh Mittal
Successive over-relaxation (SOR) is a computationally intensive, yet extremely important iterative solver for solving linear systems. Due to recent trends of exponential growth in…
A Cache Energy Optimization Technique for STT-RAM Last Level Cache
Sparsh Mittal
Last level caches (LLCs) occupy a large chip-area and there size is expected to grow further to offset the limitations of memory bandwidth and speed. Due to high leakage consumptio…
A Technique for Efficiently Managing SRAM-NVM Hybrid Cache
Sparsh Mittal
In this paper, we present a SRAM-PCM hybrid cache design, along with a cache replacement policy, named dead fast block (DFB) to manage the hybrid cache. This design aims to leverag…
A Technique for Write-endurance aware Management of Resistive RAM Last Level Caches
Sparsh Mittal
Due to increasing cache sizes and large leakage consumption of SRAM device, conventional SRAM caches contribute significantly to the processor power consumption. Recently researche…
Using Cache-coloring to Mitigate Inter-set Write Variation in Non-volatile Caches
Sparsh Mittal
In recent years, researchers have explored use of non-volatile devices such as STT-RAM (spin torque transfer RAM) for designing on-chip caches, since they provide high density and…
Dynamic cache reconfiguration based techniques for improving cache energy efficiency
Sparsh Mittal
Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage…