activity
20172025
most citedSealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption

22 citations · 30 across the 12 of their papers we have counts for

collaborators

12 papers

cs.AR2025

SAIL: SRAM-Accelerated LLM Inference System with Lookup-Table-based GEMV

Jingyao Zhang, Jaewoo Park, Jongeun Lee +1

Large Language Model (LLM) inference requires substantial computational resources, yet CPU-based inference remains essential for democratizing AI due to the widespread availability…

cs.AR2025

No One-Size-Fits-All: A Workload-Driven Characterization of Bit-Parallel vs. Bit-Serial Data Layouts for Processing-using-Memory

Jingyao Zhang, Elaheh Sadredini

Processing-in-Memory (PIM) is a promising approach to overcoming the memory-wall bottleneck. However, the PIM community has largely treated its two fundamental data layouts, Bit-Pa…

cs.AR2025

A Near-Cache Architectural Framework for Cryptographic Computing

Jingyao Zhang, Elaheh Sadredini

Recent advancements in post-quantum cryptographic algorithms have led to their standardization by the National Institute of Standards and Technology (NIST) to safeguard information…

cs.CR2025

CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing

Jingyao Zhang, Elaheh Sadredini

Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which r…

cs.CR2025

FuSeFL: Fully Secure and Scalable Federated Learning

Sahar Ghoflsaz Ghinani, Elaheh Sadredini

Federated Learning (FL) enables collaborative model training without centralizing client data, making it attractive for privacy-sensitive domains. While existing approaches employ…

cs.CR2025

Enabling Low-Cost Secure Computing on Untrusted In-Memory Architectures

Sahar Ghoflsaz Ghinani, Jingyao Zhang, Elaheh Sadredini

Modern computing systems are limited in performance by the memory bandwidth available to processors, a problem known as the memory wall. Processing-in-Memory (PIM) promises to subs…

cs.DC2024★ 1 cited

GPUVM: GPU-driven Unified Virtual Memory

Nurlan Nazaraliyev, Elaheh Sadredini, Nael Abu-Ghazaleh

Graphics Processing Units (GPUs) leverage massive parallelism and large memory bandwidth to support high-performance computing applications, such as multimedia rendering, crypto-mi…

cs.AR2023

BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication

Jingyao Zhang, Mohsen Imani, Elaheh Sadredini

Number Theoretic Transform (NTT) is an essential mathematical tool for computing polynomial multiplication in promising lattice-based cryptography. However, costly division operati…

cs.CR2022★ 7 cited

Inhale: Enabling High-Performance and Energy-Efficient In-SRAM Cryptographic Hash for IoT

Jingyao Zhang, Elaheh Sadredini

In the age of big data, information security has become a major issue of debate, especially with the rise of the Internet of Things (IoT), where attackers can effortlessly obtain p…

cs.CR2022★ 22 cited

Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption

Jingyao Zhang, Hoda Naghibijouybari, Elaheh Sadredini

To provide data and code confidentiality and reduce the risk of information leak from memory or memory bus, computing systems are enhanced with encryption and decryption engine. De…

cs.DC2017

An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture

Elaheh Sadredini, Reza Rahimi, Paniz Foroutan +2

By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the incr…

cs.DC2017

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint

Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy +1

This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furth…