2 papers
cs.DC2017
An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture
Elaheh Sadredini, Reza Rahimi, Paniz Foroutan +2
By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the incr…
cs.DC2017
Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint
Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy +1
This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furth…