118 citations · 388 across the 21 of their papers we have counts for
22 papers
OpenMP Meta-Lowering: A Declarative Approach to Performance Portable Parallel Code Generation
Luca Parigi, Giuseppe Tagliavini
The increasing diversity of parallel hardware challenges existing compilation flows. While OpenMP provides a portable abstraction for shared-memory parallelism, existing compilers…
Parallelization is All System Identification Needs: End-to-end Vibration Diagnostics on a multi-core RISC-V edge device
Amirhossein Kiamarzi, Amirhossein Moallemi, Federica Zonzini +3
The early detection of structural malfunctions requires the installation of real-time monitoring systems ensuring continuous access to the damage-sensitive information; nevertheles…
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti +11
Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumpt…
Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience
Francesco Conti, Angelo Garofalo, Davide Rossi +2
Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-sou…
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters
Jie Chen, Igor Loi, Eric Flamand +3
High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) has r…
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
Luca Valente, Yvan Tortorella, Mattia Sinigaglia +4
IoT applications span a wide range in performance and memory footprint, under tight cost and power constraints. High-end applications rely on power-hungry Systems-on-Chip (SoCs) fe…
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture
Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo +4
The demand for computation resources and energy efficiency of Convolutional Neural Networks (CNN) applications requires a new paradigm to overcome the "Memory Wall". Analog In-Memo…
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference
Nazareno Bruschi, Giuseppe Tagliavini, Francesco Conti +7
Analog In-Memory Computing (AIMC) is emerging as a disruptive paradigm for heterogeneous computing, potentially delivering orders of magnitude better peak performance and efficienc…
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors
Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini +3
The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based…
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini +4
Computationally intensive algorithms such as Deep Neural Networks (DNNs) are becoming killer applications for edge devices. Porting heavily data-parallel algorithms on resource-con…
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Davide Rossi, Francesco Conti, Manuel Eggimann +9
The Internet-of-Things requires end-nodes with ultra-low-power always-on capability for a long battery lifetime, as well as high performance, energy efficiency, and extreme flexibi…
DNN is not all you need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors
Enrico Tabanelli, Giuseppe Tagliavini, Luca Benini
Machine Learning (ML) functions are becoming ubiquitous in latency- and privacy-sensitive IoT applications, prompting a shift toward near-sensor processing at the extreme edge and…
Towards Long-term Non-invasive Monitoring for Epilepsy via Wearable EEG Devices
Thorir Mar Ingolfsson, Andrea Cossettini, Xiaying Wang +5
We present the implementation of seizure detection algorithms based on a minimal number of EEG channels on a parallel ultra-low-power embedded platform. The analyses are based on t…
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers
Emanuele Parisi, Francesco Barchi, Andrea Bartolini +2
The analysis of source code through machine learning techniques is an increasingly explored research topic aiming at increasing smartness in the software toolchain to exploit moder…
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti +2
This work introduces lightweight extensions to the RISC-V ISA to boost the efficiency of heavily Quantized Neural Network (QNN) inference on microcontroller-class cores. By extendi…
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference
Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini +3
Low bit-width Quantized Neural Networks (QNNs) enable deployment of complex machine learning models on constrained devices such as microcontrollers (MCUs) by reducing their memory…
A transprecision floating-point cluster for efficient near-sensor data analytics
Fabio Montagna, Stefan Mach, Simone Benatti +5
Recent applications in the domain of near-sensor computing require the adoption of floating-point arithmetic to reconcile high precision results with a wide dynamic range. In this…
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs
Alessio Burrello, Angelo Garofalo, Nazareno Bruschi +3
The deployment of Deep Neural Networks (DNNs) on end-nodes at the extreme edge of the Internet-of-Things is a critical enabler to support pervasive Deep Learning-enhanced applicati…
Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices
Nazareno Bruschi, Angelo Garofalo, Francesco Conti +2
The deployment of Quantized Neural Networks (QNN) on advanced microcontrollers requires optimized software to exploit digital signal processing (DSP) extensions of modern instructi…
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters
Florian Glaser, Giuseppe Tagliavini, Davide Rossi +3
The steeply growing performance demands for highly power- and energy-constrained processing systems such as end-nodes of the internet-of-things (IoT) have led to parallel near-thre…
Combining Learning and Optimization for Transprecision Computing
Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi +2
The growing demands of the worldwide IT infrastructure stress the need for reduced power consumption, which is addressed in so-called transprecision computing by improving energy e…
A Transprecision Floating-Point Platform for Ultra-Low Power Computing
Giuseppe Tagliavini, Stefan Mach, Davide Rossi +2
In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor to the energy consumption of compute-intensive applications with large dynamic…