3 papers
cs.AR2025
Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Zhexuan Xu, Kexin Zhou, Jie Wang +5
Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of…
cs.RO2025
One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner
Zhexuan Xu, Jie Wang, Siyuan Xu +3
Floorplanning determines the shapes and locations of modules on a chip canvas and plays a critical role in optimizing the chip's Power, Performance, and Area (PPA) metrics. However…
cs.AR2024
Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
Zhihai Wang, Zijie Geng, Zhaojie Tu +12
The increasing complexity of modern very-large-scale integration (VLSI) design highlights the significance of Electronic Design Automation (EDA) technologies. Chip placement is a c…