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20162026
most citedOn-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

79 citations · 208 across the 29 of their papers we have counts for

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Showing 2024Show all

5 papers · 1 filter

cs.AR2024★ 2 cited

MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures

Lukas Pfromm, Alish Kanani, Harsh Sharma +6

Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D design technologies approach thei…

cs.AR2024

HeTraX: Energy Efficient 3D Heterogeneous Manycore Architecture for Transformer Acceleration

Pratyush Dhingra, Janardhan Rao Doppa, Partha Pratim Pande

Transformers have revolutionized deep learning and generative modeling to enable unprecedented advancements in natural language processing tasks and beyond. However, designing hard…

cs.AR2024

Look-Up Table based Neural Network Hardware

Ovishake Sen, Chukwufumnanya Ogbogu, Peyman Dehghanzadeh +4

Traditional digital implementations of neural accelerators are limited by high power and area overheads, while analog and non-CMOS implementations suffer from noise, device mismatc…

cs.AR2024

Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads

Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa +2

Processing-in-memory (PIM) has emerged as an enabler for the energy-efficient and high-performance acceleration of deep learning (DL) workloads. Resistive random-access memory (ReR…

cs.AR2024★ 2 cited

FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators

Pratyush Dhingra, Chukwufumnanya Ogbogu, Biresh Kumar Joardar +3

Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture is an attractive solution for training Graph Neural Networks (GNNs) on edge platforms. However,…