activity
20242026
collaborators

8 papers

cs.AI2026

EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair

Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang +2

Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often…

quant-ph2026

LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout

M. A. Farooq, G. Di Guglielmo, A. Rajagopala +3

Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recent…

cs.AR2026

GR-Evolve: Design-Adaptive Global Routing via LLM-Driven Algorithm Evolution

Taizun Jafri, Vidya A. Chhabria

Modern ASIC design is becoming increasingly complex, driving up design costs while limiting productivity gains from existing EDA tools. Despite decades of progress, current tools r…

cs.LG2025

DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design

Bing-Yue Wu, Vidya A. Chhabria

Machine learning (ML) has demonstrated significant promise in various physical design (PD) tasks. However, model generalizability remains limited by the availability of high-qualit…

cs.AR2025

CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs

Jiajun Hu, Chetan Choppali Sudarshan, Vidya A. Chhabria +1

Over the years, the chip industry has consistently developed high-performance processors to address the increasing demands across diverse applications. However, the rapid expansion…

cs.AR2024

IR-Aware ECO Timing Optimization Using Reinforcement Learning

Wenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar

Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analys…