3.1k citations · 3.9k across the 11 of their papers we have counts for
14 papers
SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables on-the-fly variable SIMD vector-length
Ashish Shrivastava, Alan Gatherer, Tong Sun +2
Over the last decade the relative latency of access to shared memory by multicore increased as wire resistance dominated latency and low wire density layout pushed multiport memori…
Towards a Domain Specific Solution for a New Generation of Wireless Modems
Alan Gatherer, Ashish Shrivastava, Hao Luan +3
Wireless cellular System on Chip (SoC) are experiencing unprecedented demands on data rate, latency use case variety. 5G wireless technologies require a massive number of antennas…
Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture
Hao Luan, Alan Gatherer
Manycore SoC architectures based on on-chip shared memory are preferred for flexible and programmable solutions in many application domains. However, the development of many ported…
Advanced Receiver Architectures for Millimeter Wave Communications with Low-Resolution ADCs
Jinseok Choi, Gilwon Lee, Ahmed Alkhateeb +3
Employing low-resolution analog-to-digital converters (ADCs) for millimeter wave receivers with large antenna arrays provides opportunity to efficiently reduce power consumption of…
Base Station Antenna Selection for Low-Resolution ADC Systems
Jinseok Choi, Junmo Sung, Narayan Prasad +3
This paper investigates antenna selection at a base station with large antenna arrays and low-resolution analog-to-digital converters. For downlink transmit antenna selection for n…
Robust Learning-Based ML Detection for Massive MIMO Systems with One-Bit Quantized Signals
Jinseok Choi, Yunseong Cho, Brian L. Evans +1
In this paper, we investigate learning-based maximum likelihood (ML) detection for uplink massive multiple-input and multiple-output (MIMO) systems with one-bit analog-to-digital c…