52 citations · 282 across the 12 of their papers we have counts for
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cs.CR2017★ 28 cited
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
Satwik Patnaik, Mohammed Ashraf, Johann Knechtel +1
Layout camouflaging (LC) is a promising technique to protect chip design intellectual property (IP) from reverse engineers. Most prior art, however, cannot leverage the full potent…
cs.CR2017★ 30 cited
Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques
Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel +3
Split manufacturing is a promising technique to defend against fab-based malicious activities such as IP piracy, overbuilding, and insertion of hardware Trojans. However, a network…