23 citations · 74 across the 16 of their papers we have counts for
11 papers · 1 filter
Hardware Mechanisms to Dynamically Throttle AI Performance
Haiyue Ma, Lauren Malek, Joseph Forzani +1
As more capable AI models are increasingly integrated into critical computer systems, the lack of control over AI intent motivates safety mechanisms. Existing software safeguards i…
SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
Hengrui Zhang, Pratyush Patel, August Ning +1
Large Language Models (LLMs) have gained popularity in recent years, driving up the demand for inference. LLM inference is composed of two phases with distinct characteristics: a c…
A Hardware Evaluation Framework for Large Language Model Inference
Hengrui Zhang, August Ning, Rohan Prabhakar +1
The past year has witnessed the increasing popularity of Large Language Models (LLMs). Their unprecedented scale and associated high hardware cost have impeded their broader adopti…
Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi +1
The design space exploration of scaled-out manycores for communication-intensive applications (e.g., graph analytics and sparse linear algebra) is hampered due to either lack of sc…
Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff +1
Graph search and sparse data-structure traversal workloads contain challenging irregular memory patterns on global data structures that need to be modified atomically. Distributed…
DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi +1
In recent years, the growing demand to process large graphs and sparse datasets has led to increased research efforts to develop hardware- and software-based architectural solution…
Using LLMs to Facilitate Formal Verification of RTL
Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff
Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as Sy…
Duet: Creating Harmony between Processors and Embedded FPGAs
Ang Li, August Ning, David Wentzlaff
The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained ac…
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff +1
Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor cor…
AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff +1
Modern SoC design relies on the ability to separately verify IP blocks relative to their own specifications. Formal verification (FV) using SystemVerilog Assertions (SVA) is an eff…
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
Katie Lim, Jonathan Balkind, David Wentzlaff
Energy efficiency has become an increasingly important concern in computer architecture due to the end of Dennard scaling. Heterogeneity has been explored as a way to achieve bette…