150 citations · 150 across the 4 of their papers we have counts for
4 papers · 1 filter
DL-PIM: Improving Data Locality in Processing-in-Memory Systems
Parker Hao Tian, Zahra Yousefijamarani, Alaa Alameldeen
PIM architectures aim to reduce data transfer costs between processors and memory by integrating processing units within memory layers. Prior PIM architectures have shown potential…
Speculative Interference Attacks: Breaking Invisible Speculation Schemes
Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella +13
Recent security vulnerabilities that target speculative execution (e.g., Spectre) present a significant challenge for processor design. The highly publicized vulnerability uses spe…
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism
K. K. Chang, D. Lee, Z. Chishti +4
This article summarizes the idea of "refresh-access parallelism," which was published in HPCA 2014, and examines the work's significance and future potential. The overarching objec…
Improving DRAM Performance by Parallelizing Refreshes with Accesses
Kevin K. Chang, Donghyuk Lee, Zeshan Chishti +4
Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR DRAM refreshes cells at the rank level. This degrades performance significantly beca…