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Luis Vitorio Cargnini

LIRMM, Samsung, WD, HGST, Micron

3 papers hereh-index 8222 citations14 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author2

Across the 2 of 3 papers where every author was matched, so the position is known.

fields
  • cs.AR2
  • cs.OS1
affiliations
  • LIRMM, Samsung, WD, HGST, Micron

identity via Semantic Scholar / OpenAlex

activity
20172026
collaborators
Showing cs.ARShow all

2 papers · 1 filter

cs.AR2026

CMM-MP: A Novel Memory Pooling Architecture using Purpose-built Memory Device with CXL and Ethernet

Michael Wasef, Gongjin Sun, Edmund Au +15

CXL Memory Module - Memory Pooling (CMM-MP) introduces a novel memory pooling architecture to meet the unique requirements of emerging memory-intensive workloads. This industry-fir…

cs.AR2024

ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model

Hanqiu Chen, Yitu Wang, Luis Vitorio Cargnini +7

Compute Express Link (CXL) emerges as a solution for wide gap between computational speed and data communication rates among host and multiple devices. It fosters a unified and coh…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.