3 papers
cs.CR2025
VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog
Xiang Long, Yingjie Xia, Xiyuan Chen +1
Timely detection of hardware vulnerabilities during the early design stage is critical for reducing remediation costs. Existing early detection techniques often require specialized…
cs.CR2025
SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
Ziteng Hu, Yingjie Xia, Xiyuan Chen +1
Finite State Machines (FSMs) play a critical role in implementing control logic for Systems-on-Chip (SoC). Traditionally, FSMs are implemented by hardware engineers through Verilog…
cs.AR2025
ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models
Wenhao Lv, Yingjie Xia, Xiyuan Chen +1
In modern Very Large Scale Integrated (VLSI) circuit design flow, the Register-Transfer Level (RTL) stage presents a critical opportunity for timing optimization. Addressing timing…