6 papers
ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
Bingkun Yao, Ning Wang, Xiangfeng Liu +5
Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this e…
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
Ning Wang, Bingkun Yao, Jie Zhou +4
Large Language Models (LLMs) have demonstrated remarkable potential in debugging for various programming languages. However, the application of LLMs to Verilog debugging remains in…
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
Ning Wang, Bingkun Yao, Jie Zhou +4
Large language models (LLMs) have shown strong performance in Verilog generation from natural language description. However, ensuring the functional correctness of the generated co…
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
Ning Wang, Bingkun Yao, Jie Zhou +3
Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Veril…
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Jie Zhou, Youshu Ji, Ning Wang +7
SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours…
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou +4
Bug localization in Verilog code is a crucial and time-consuming task during the verification of hardware design. Since introduction, Large Language Models (LLMs) have showed their…