3 papers
cs.AR2025
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation
Anjiang Wei, Huanmi Tan, Tarun Suresh +5
Recent advances in Large Language Models (LLMs) have sparked growing interest in applying them to Electronic Design Automation (EDA) tasks, particularly Register Transfer Level (RT…
cs.CR2025
Analyzing and Exploiting Branch Mispredictions in Microcode
Nicholas Mosier, Hamed Nemati, John C. Mitchell +1
We present uSpectre, a new class of transient execution attacks that exploit microcode branch mispredictions to transiently leak sensitive data. We find that many long-known and re…
cs.CR2024
RTL2MPATH: Multi-PATH Synthesis with Applications to Hardware Security Verification
Yao Hsiao, Nikos Nikoleris, Artem Khyzha +4
The Check tools automate formal memory consistency model and security verification of processors by analyzing abstract models of microarchitectures, called SPEC models. Despite…