3 papers
cs.AR2026
Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core
Benjamin Hubinet, Pierre-Alain Moellic, Olivier Savry +2
By leveraging standard RISC-V extensions, namely Zfh (scalar float16) and Zvfh (vector float16), this work proposes an open-source framework to enable complete on-device training o…
cs.AR2025
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart +11
Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on t…
cs.AR2024
Using a Performance Model to Implement a Superscalar CVA6
Côme Allart, Jean-Roch Coulon, André Sintzoff +2
A performance model of CVA6 RISC-V processor is built to evaluate performance related modifications before implementing them in RTL. Its accuracy is 99.2% on CoreMark. This model i…