3 papers
cs.AR2025
Re-thinking Memory-Bound Limitations in CGRAs
Xiangfeng Liu, Zhe Jiang, Anzhen Zhu +4
Coarse-Grained Reconfigurable Arrays (CGRAs) are specialized accelerators commonly employed to boost performance in workloads with iterative structures. Existing research typically…
cs.SE2025
ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
Bingkun Yao, Ning Wang, Xiangfeng Liu +5
Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this e…
cs.AI2025
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Juxin Niu, Xiangfeng Liu, Dan Niu +3
Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is incre…