2 papers
cs.SE2025
A Multi-stage Error Diagnosis for APB Transaction
Cheng-Yang Tsai, Tzu-Wei Huang, Jen-Wei Shih +3
Functional verification and debugging are critical bottlenecks in modern System-on-Chip (SoC) design, with manual detection of Advanced Peripheral Bus (APB) transaction errors in l…
cs.AR2025
Subitizing-Inspired_Large_Language_Models_for_Floorplanning
Shao-Chien Lu, Chen-Chen Yeh, Hui-Lin Cho +2
We present a novel approach to solving the floorplanning problem by leveraging fine-tuned Large Language Models (LLMs). Inspired by subitizing--the human ability to instantly and a…