4 papers
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
Zhongzhi Yu, Mingjie Liu, Michael Zimmer +3
Despite recent progress in generating hardware RTL code with LLMs, existing solutions still suffer from a substantial gap between practical application scenarios and the requiremen…
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Nathaniel Pinckney, Chenhui Deng, Chia-Tung Ho +5
We present the Comprehensive Verilog Design Problems (CVDP) benchmark, a new dataset and infrastructure to advance LLM and agent research in hardware design and verification. CVDP…
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
Mingjie Liu, Yun-Da Tsai, Wenfei Zhou +1
Despite the significant progress made in code generation with large language models, challenges persist, especially with hardware description languages such as Verilog. This paper…
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware
Minwoo Kang, Mingjie Liu, Ghaith Bany Hamad +2
The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital ch…