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cs.AR2025
SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
Rishab Parthasarathy
Solving sparse systems of linear equations is a fundamental problem in the field of numerical methods, with applications spanning from circuit design to urban planning. These probl…
cs.AR2025
always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission
Rishab Parthasarathy, Akshay Attaluri, Gilford Ting
We present a design for an extensible video conferencing stack implemented entirely in hardware on a Nexys4 DDR FPGA, which uses the M-JPEG codec to compress video and a UDP networ…