2 papers
cs.AR2026
Benchmarking LLMs for Verilog Design Flows
Angshuman Chakravertty, Rahul Koshti, Buddhi Prakash Sharma +1
Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be p…
cs.CR2025
FAST-IDS: A Fast Two-Stage Intrusion Detection System with Hybrid Compression for Real-Time Threat Detection in Connected and Autonomous Vehicles
Devika S, Vishnu Hari, Pratik Narang +2
We have implemented a multi-stage IDS for CAVs that can be deployed to resourec-constrained environments after hybrid model compression.