activity
20172022
most citedEfficient Error-Tolerant Quantized Neural Network Accelerators

39 citations · 47 across the 6 of their papers we have counts for

collaborators

8 papers

cs.LG20221 cited

EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators

Lois Orosa, Skanda Koppula, Yaman Umuroglu +5

Dilated and transposed convolutions are widely used in modern convolutional neural networks (CNNs). These kernels are used extensively during CNN training and inference of applicat…

cs.LG2020

FAT: Training Neural Networks for Reliable Inference Under Hardware Faults

Ussama Zahid, Giulio Gambardella, Nicholas J. Fraser +2

Deep neural networks (DNNs) are state-of-the-art algorithms for multiple applications, spanning from image classification to speech recognition. While providing excellent accuracy,…

cs.DC2020

Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine

Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss +2

Xilinx's AI Engine is a recent industry example of energy-efficient vector processing that includes novel support for 2D SIMD datapaths and shuffle interconnection network. The cur…

eess.SP201939 cited

Efficient Error-Tolerant Quantized Neural Network Accelerators

Giulio Gambardella, Johannes Kappauf, Michaela Blott +4

Neural Networks are currently one of the most widely deployed machine learning algorithms. In particular, Convolutional Neural Networks (CNNs), are gaining popularity and are evalu…

cs.CV20191 cited

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels

Murad Qasaimeh, Kristof Denolf, Jack Lo +3

Developing high performance embedded vision applications requires balancing run-time performance with energy constraints. Given the mix of hardware accelerators that exist for embe…

cs.CV2018

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

Yifan Yang, Qijing Huang, Bichen Wu +8

Using FPGAs to accelerate ConvNets has attracted significant attention in recent years. However, FPGA accelerator design has not leveraged the latest progress of ConvNets. As a res…