67 citations · 80 across the 4 of their papers we have counts for
5 papers
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou +3
We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier,…
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency
Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou +3
Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. W…
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
Julian Faraone, Martin Kumm, Martin Hardieck +4
Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potenti…
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks
Julian Faraone, Nicholas Fraser, Giulio Gambardella +2
A low precision deep neural network training technique for producing sparse, ternary neural networks is presented. The technique incorporates hard- ware implementation costs during…
Scaling Binarized Neural Networks on Reconfigurable Logic
Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella +4
Binarized neural networks (BNNs) are gaining interest in the deep learning community due to their significantly lower computational and memory cost. They are particularly well suit…