2 papers
cs.AR2025
ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation
Daniel Ruelas-Petrisko, Farzam Gilani, Anoop Mysore Nataraja +2
As processors increase in complexity, costs grow even more rapidly, both for functional verification and performance validation. Most often, silicon characterizations comprise simp…
cs.PL2024
Scaling Program Synthesis Based Technology Mapping with Equality Saturation
Gus Henry Smith, Colin Knizek, Daniel Petrisko +5
State-of-the-art hardware compilers for FPGAs often fail to find efficient mappings of high-level designs to low-level primitives, especially complex programmable primitives like d…