78 citations · 222 across the 36 of their papers we have counts for
6 papers · 2 filters
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu +4
The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are int…
Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
Robert Guirado, Hyoukjun Kwon, Sergi Abadal +2
Deep neural network (DNN) models continue to grow in size and complexity, demanding higher computational power to enable real-time inference. To efficiently deliver such computatio…
ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning
Sheng-Chun Kao, Geonhwa Jeong, Tushar Krishna
DNN accelerators provide efficiency by leveraging reuse of activations/weights/outputs during the DNN computations to reduce data movement from DRAM to the chip. The reuse is captu…
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics
Brian Crafton, Samuel Spetalnick, Gauthaman Murali +3
Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has fou…
The gem5 Simulator: Version 20.0+
Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram +75
The open-source and community-supported gem5 simulator is one of the most popular tools for computer architecture research. This simulation infrastructure allows researchers to mod…
Enabling Compute-Communication Overlap in Distributed Deep Learning Training Platforms
Saeed Rashidi, Matthew Denton, Srinivas Sridharan +4
Deep Learning (DL) training platforms are built by interconnecting multiple DL accelerators (e.g., GPU/TPU) via fast, customized interconnects with 100s of gigabytes (GBs) of bandw…