82 citations · 199 across the 12 of their papers we have counts for
6 papers · 1 filter
ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multipliers
Ao Ren, Tianyun Zhang, Shaokai Ye +5
To facilitate efficient embedded and hardware implementations of deep neural networks (DNNs), two important categories of DNN model compression techniques: weight pruning and weigh…
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks using Stochastic Computing
Zhe Li, Ji Li, Ao Ren +5
Recently, Deep Convolutional Neural Network (DCNN) has achieved tremendous success in many machine learning applications. Nevertheless, the deep structure has brought significant i…
Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs
Caiwen Ding, Ao Ren, Geng Yuan +5
Both industry and academia have extensively investigated hardware accelerations. In this work, to address the increasing demands in computational capability and memory requirement,…
An Area and Energy Efficient Design of Domain-Wall Memory-Based Deep Convolutional Neural Networks using Stochastic Computing
Xiaolong Ma, Yipeng Zhang, Geng Yuan +5
With recent trend of wearable devices and Internet of Things (IoTs), it becomes attractive to develop hardware-based deep convolutional neural networks (DCNNs) for embedded applica…
Algorithm-Hardware Co-Optimization of the Memristor-Based Framework for Solving SOCP and Homogeneous QCQP Problems
Ao Ren, Sijia Liu, Ruizhe Cai +3
A memristor crossbar, which is constructed with memristor devices, has the unique ability to change and memorize the state of each of its memristor elements. It also has other high…
VIBNN: Hardware Acceleration of Bayesian Neural Networks
Ruizhe Cai, Ao Ren, Ning Liu +5
Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probabi…