activity
20162026
most citedHardware for Machine Learning: Challenges and Opportunities

192 citations · 572 across the 26 of their papers we have counts for

collaborators

28 papers

cs.AR2026

AccelForge: Comprehensive Modeling and Co-Design Framework for AI Accelerators

Tanner Andrulis, Michael Gilbert, Vivienne Sze +1

Tensor algebra workloads, of which deep neural networks are prominent examples, are energy-intensive workloads in modern datacenter and edge deployments, making accelerators necess…

cs.DS2026

The Einsum-Enabled Design Space for Graph Algorithms: A BFS Case Study

Toluwanimi O. Odemuyiwa, Serban D. Porumbescu, Muhammad Osama +2

We propose a principled approach to reasoning about various graph algorithm implementations. We leverage the extended general Einsum notation (EDGE) which allows us to factor compl…

cs.PF2026

Campaign Diagrams: Visualizing the March Through the Phases of a Workload

Toluwanimi O. Odemuyiwa, John D. Owens, Michael Pellauer +1

We present campaign diagrams, a visualization technique for phase-level analysis of resource utilization and bottlenecks in modern workloads. Existing tools have a trade-off: roofl…

cs.AR2026

Mambalaya: Einsum-Based Fusion Optimizations on State-Space Models

Toluwanimi O. Odemuyiwa, John D. Owens, Joel S. Emer +1

Mamba is an emerging, complex workload with various short-range and long-range dependencies, nonlinearities, and elementwise computations that are unable to run at near-peak speeds…

cs.AR2026

The Turbo-Charged Mapper: Fast and Optimal Mapping for Energy-efficient and Low-latency Accelerator Design

Michael Gilbert, Tanner Andrulis, Vivienne Sze +1

The energy and latency of an accelerator running a deep neural network (DNN) depend on how the computation and data movement are scheduled in the accelerator (i.e., mapping), and p…

cs.AR2026

Fast and Fusiest: An Optimal Fusion-Aware Mapper for Accelerator Design

Tanner Andrulis, Michael Gilbert, Vivienne Sze +1

A low-latency and energy-efficient tensor algebra accelerator design must optimize how data movement and operations are scheduled (i.e., mapped) in the accelerator architecture. A…

cs.PL2025

Insum: Sparse GPU Kernels Simplified and Optimized with Indirect Einsums

Jaeyeon Won, Willow Ahrens, Joel S. Emer +1

Programming high-performance sparse GPU kernels is notoriously difficult, requiring both substantial effort and deep expertise. Sparse compilers aim to simplify this process, but e…

cs.AR2024

LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space

Michael Gilbert, Yannan Nellie Wu, Joel S. Emer +1

Latency and energy consumption are key metrics in the performance of deep neural network (DNN) accelerators. A significant factor contributing to latency and energy is data transfe…

cs.PL2024★ 1 cited

The Continuous Tensor Abstraction: Where Indices are Real

Jaeyeon Won, Willow Ahrens, Teodoro Fields Collin +2

This paper introduces the continuous tensor abstraction, allowing indices to take real-number values (for example, A[3.14]). It also presents continuous tensor algebra expressions,…

cs.AR2024★ 9 cited

FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design

Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa +3

Attention for transformers is a critical workload that has recently received significant "attention" as a target for custom acceleration. Yet, while prior work succeeds in reducing…

cs.AR2024★ 30 cited

CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool

Tanner Andrulis, Joel S. Emer, Vivienne Sze

Compute-In-Memory (CiM) is a promising solution to accelerate Deep Neural Networks (DNNs) as it can avoid energy-intensive DNN weight movement and use memory arrays to perform low-…

cs.ET2024★ 5 cited

Architecture-Level Modeling of Photonic Deep Neural Network Accelerators

Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M. Suriyakumar +2

Photonics is a promising technology to accelerate Deep Neural Networks as it can use optical interconnects to reduce data movement energy and it enables low-energy, high-throughput…

cs.AR2024★ 3 cited

Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design

Tanner Andrulis, Ruicong Chen, Hae-Seung Lee +2

Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so archi…

cs.DS2024★ 1 cited

The EDGE Language: Extended General Einsums for Graph Algorithms

Toluwanimi O. Odemuyiwa, Serban D. Porumbescu, Nandeeka Nayak +3

In this work, we propose a unified abstraction for graph algorithms: the Extended General Einsums language, or EDGE. The EDGE language expresses graph algorithms in the language of…

cs.AR2023★ 11 cited

Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity

Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer +1

Sparse tensor algebra is a challenging class of workloads to accelerate due to low arithmetic intensity and varying sparsity patterns. Prior sparse tensor algebra accelerators have…

cs.CR2023★ 1 cited

Penetrating Shields: A Systematic Analysis of Memory Corruption Mitigations in the Spectre Era

Weon Taek Na, Joel S. Emer, Mengjia Yan

This paper provides the first systematic analysis of a synergistic threat model encompassing memory corruption vulnerabilities and microarchitectural side-channel vulnerabilities.…

cs.AR2023★ 28 cited

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity

Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan +3

Due to complex interactions among various deep neural network (DNN) optimization techniques, modern DNNs can have weights and activations that are dense or sparse with diverse spar…

cs.AR2023★ 45 cited

RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!

Tanner Andrulis, Joel S. Emer, Vivienne Sze

Processing-In-Memory (PIM) accelerators have the potential to efficiently run Deep Neural Network (DNN) inference by reducing costly data movement and by using resistive RAM (ReRAM…

cs.AR2023★ 19 cited

TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators

Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare +3

Over the past few years, the explosion in sparse tensor algebra workloads has led to a corresponding rise in domain-specific accelerators to service them. Due to the irregularity p…

cs.AR2022★ 38 cited

The Sparse Abstract Machine

Olivia Hsu, Maxwell Strange, Ritvik Sharma +5

We propose the Sparse Abstract Machine (SAM), an abstract machine model for targeting sparse tensor algebra to reconfigurable and fixed-function spatial dataflow accelerators. SAM…

cs.AR2022★ 2 cited

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar +2

In recent years, many accelerators have been proposed to efficiently process sparse tensor algebra applications (e.g., sparse neural networks). However, these proposals are single…

cs.ET2020

Freely scalable and reconfigurable optical hardware for deep learning

Liane Bernstein, Alexander Sludds, Ryan Hamerly +3

As deep neural network (DNN) models grow ever-larger, they can achieve higher accuracy and solve more complex problems. This trend has been enabled by an increase in available comp…

cs.DC2020★ 2 cited

Estimating Silent Data Corruption Rates Using a Two-Level Model

Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai +7

High-performance and safety-critical system architects must accurately evaluate the application-level silent data corruption (SDC) rates of processors to soft errors. Such an evalu…

cs.DC2018★ 11 cited

Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices

Yu-Hsin Chen, Tien-Ju Yang, Joel Emer +1

A recent trend in DNN development is to extend the reach of deep learning applications to platforms that are more resource and energy constrained, e.g., mobile devices. These endea…