11 citations · 16 across the 9 of their papers we have counts for
9 papers
ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures
Abishek Ramdas, Michael Giardino, Runbin Shi +4
Unlike other accelerators, FPGAs are capable of supporting cache coherency, thereby turning them into a more powerful architectural option than just a peripheral accelerator. Howev…
Secure Memory Management on Modern Hardware
Reto Achermann, Nora Hossle, Lukas Humbel +3
Almost all modern hardware, from phone SoCs to high-end servers with accelerators, contain memory translation and protection hardware like IOMMUs, firewalls, and lookup tables whic…
CleanQ: a lightweight, uniform, formally specified interface for intra-machine data transfer
Roni Haecki, Lukas Humbel, Reto Achermann +3
We present CleanQ, a high-performance operating-system interface for descriptor-based data transfer with rigorous formal semantics, based on a simple, formally-verified notion of o…
Cichlid: Explicit physical memory management for large machines
Simon Gerber, Gerd Zellweger, Reto Achermann +4
In this paper, we rethink how an OS supports virtual memory. Classical VM is an opaque abstraction of RAM, backed by demand paging. However, most systems today (from phones to data…
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
Reto Achermann, Ashish Panwar, Abhishek Bhattacharjee +2
Multi-socket machines with 1-100 TBs of physical memory are becoming prevalent. Applications running on multi-socket machines suffer non-uniform bandwidth and latency when accessin…
A Least-Privilege Memory Protection Model for Modern Hardware
Reto Achermann, Nora Hossle, Lukas Humbel +3
We present a new least-privilege-based model of addressing on which to base memory management functionality in an OS for modern computers like phones or server-based accelerators.…