collaborators

5 papers

cs.AR2024

HeTraX: Energy Efficient 3D Heterogeneous Manycore Architecture for Transformer Acceleration

Pratyush Dhingra, Janardhan Rao Doppa, Partha Pratim Pande

Transformers have revolutionized deep learning and generative modeling to enable unprecedented advancements in natural language processing tasks and beyond. However, designing hard…

cs.AR2024

Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads

Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa +2

Processing-in-memory (PIM) has emerged as an enabler for the energy-efficient and high-performance acceleration of deep learning (DL) workloads. Resistive random-access memory (ReR…

cs.AR20242 cited

FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators

Pratyush Dhingra, Chukwufumnanya Ogbogu, Biresh Kumar Joardar +3

Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture is an attractive solution for training Graph Neural Networks (GNNs) on edge platforms. However,…

cs.AR2023

Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators

Xueying Wu, Edward Hanson, Nansu Wang +9

Resistive random access memory (ReRAM)-based processing-in-memory (PIM) architectures have demonstrated great potential to accelerate Deep Neural Network (DNN) training/inference.…

cs.ET2016

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip

Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande +1

A three-dimensional (3D) Network-on-Chip (NoC) enables the design of high performance and low power many-core chips. Existing 3D NoCs are inadequate for meeting the ever-increasing…