4 papers
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak +2
Microarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental security assumptions. They leverage timing variations of sever…
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance
Matteo Perotti, Vincenzo Maisto, Moritz Imfeld +3
Vector processor architectures offer an efficient solution for accelerating data-parallel workloads (e.g., ML, AI), reducing instruction count, and enhancing processing efficiency.…
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Matteo Perotti, Matheus Cavalcante, Nils Wistoff +3
Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips,…
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
Enrico Zelioli, Alessandro Ottaviano, Robert Balas +3
The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands of modern autonomous systems require advanced heterogeneous embedded architectures. Such a…