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cs.CL2025
Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code
Manar Abdelatty, Maryam Nouh, Jacob K. Rosenstein +1
Large Language Models (LLMs) are increasingly used to automate hardware design tasks, including the generation of Verilog code. While early benchmarks focus primarily on functional…
cs.CL2025
ChipXplore: Natural Language Exploration of Hardware Designs and Libraries
Manar Abdelatty, Jacob Rosenstein, Sherief Reda
Hardware design workflows rely on Process Design Kits (PDKs) from different fabrication nodes, each containing standard cell libraries optimized for speed, power, or density. Engin…