12 papers
VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generation
Zhuorui Zhao, Bing Li, Yu Li +2
Large language models (LLMs) have demonstrated promising capabilities in generating Verilog code from natural language specifications. However, human-written specifications often c…
LLM for EDA in Front-End Design: Challenges and Opportunities
Kangwei Xu, Bing Li, Ulf Schlichtmann
As chip complexity increases and time-to-market pressures grow, front-end design has become a critical bottleneck in chip development. Recently, Large Language Models (LLMs) have s…
CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference
Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann +1
Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency towar…
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
Zhuorui Zhao, Bing Li, Grace Li Zhang +1
Large Language Models (LLMs) have shown impressive potential in generating Verilog codes, but ensuring functional correctness remains a challenge. Existing approaches often rely on…
Large Language Models (LLMs) for Electronic Design Automation (EDA)
Kangwei Xu, Denis Schwachhofer, Jason Blocklove +10
With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involve…
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis
Kangwei Xu, Bing Li, Grace Li Zhang +1
In high-level synthesis (HLS), C/C++ programs with synthesis directives are used to generate circuits for FPGA implementations. However, hardware-specific and platform-dependent ch…