3 papers
cs.AR2025
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2
Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…
cs.AR2025
OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
Rishov Sarkar, Cong Hao
High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential…
cs.AR2024
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
Stefan Abi-Karam, Rishov Sarkar, Allison Seigler +7
Machine learning (ML) techniques have been applied to high-level synthesis (HLS) flows for quality-of-result (QoR) prediction and design space exploration (DSE). Nevertheless, the…