FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs

Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama +2

Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging.…