most citedAn Accurate Interconnect Test Structure for Parasitic Validation in On-Chip Machine Learning Accelerators

2 citations · 2 across the 2 of their papers we have counts for

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2 papers

cs.ET2017★ 2 cited

An Accurate Interconnect Test Structure for Parasitic Validation in On-Chip Machine Learning Accelerators

Chun-Chen Liu, Oscar Law, Fei Li

For nanotechnology nodes, the feature size is shrunk rapidly, the wire becomes narrow and thin, it leads to high RC parasitic, especially for resistance. The overall system perform…

cs.ET2016

Complete DFM Model for High-Performance Computing SoCs with Guard Ring and Dummy Fill Effect

Chun-Chen Liu, Oscar Lau, Jason Y. Du

For nanotechnology, the semiconductor device is scaled down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer d…