6 papers
Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories
Fabia F. Athena, Jonathan Hartanto, Matthias Passlack +11
We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semico…
High-current p-type transistors from precursor-engineered synthetic monolayer WSe
Anh Tuan Hoang, Kathryn Neilson, Kaikui Xu +11
Monolayer tungsten diselenide (WSe) is a leading candidate for nanoscale complementary logic. However, high defect densities introduced during thin-film growth and device fabri…
Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors
Robert K. A. Bennett, Jan-Lucas Uslu, Harmon F. Gault +8
We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimensional (2D) transistors from elect…
Wide-field Hyperspectral Optical Microscopy for Rapid Characterization of Two-Dimensional Semiconductors and Heterostructures
Zhenghan Peng, Adeyemi Uthman, Zhepeng Zhang +4
Electronic and optoelectronic applications of two-dimensional (2D) semiconductors demand precise control over material quality, including thickness, composition, doping, and defect…
Low Resistance P-type Contacts to Monolayer WSe through Chlorinated Solvent Doping
Lauren Hoang, Robert K. A. Bennett, Anh Tuan Hoang +7
Tungsten diselenide (WSe) is a promising p-type semiconductor limited by high contact resistance () and the lack of a reliable doping strategy. Here, we demonstra…
Mobility and Threshold Voltage Extraction in Transistors with Gate-Voltage-Dependent Contact Resistance
Robert K. A. Bennett, Lauren Hoang, Connor Cremers +2
The mobility of emerging (e.g., two-dimensional, oxide, organic) semiconductors is commonly estimated from transistor current-voltage measurements. However, such devices often expe…