Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

Fabia F. Athena, Jonathan Hartanto, Matthias Passlack +11

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semico…