3 papers
cs.CL2025
Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework
Haoyue Yang, Xuanle Zhao, Yujie Liu +5
The reproduction of hardware architectures from academic papers remains a significant challenge due to the lack of publicly available source code and the complexity of hardware des…
cs.SE2025
Isolating Compiler Bugs through Compilation Steps Analysis
Yujie Liu, Mingxuan Zhu, Shengyu Cheng +1
Compilers are essential to software systems, and their bugs can propagate to dependent software. Ensuring compiler correctness is critical. However, isolating compiler bugs remains…
cs.LG2025
Step-3 is Large yet Affordable: Model-system Co-design for Cost-effective Decoding
StepFun, :, Bin Wang +195
Large language models (LLMs) face low hardware efficiency during decoding, especially for long-context reasoning tasks. This paper introduces Step-3, a 321B-parameter VLM with hard…