109 citations · 206 across the 28 of their papers we have counts for
28 papers
Surrogates, Spikes, and Sparsity: Performance Analysis and Characterization of SNN Hyperparameters on Hardware
Ilkin Aliyev, Jesus Lopez, Tosiron Adegbija
Spiking Neural Networks (SNNs) offer inherent advantages for low-power inference through sparse, event-driven computation. However, the theoretical energy benefits of SNNs are ofte…
Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories
Yousuf Choudhary, Tosiron Adegbija
Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresi…
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
Yuchao Liao, Tosiron Adegbija, Roman Lysecky
Post-quantum cryptography (PQC) is crucial for securing data against emerging quantum threats. However, its algorithms are computationally complex and difficult to implement effici…
Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study
Yousuf Choudhary, Tosiron Adegbija
Antiferromagnetic Tunnel Junctions (AFMTJs) enable picosecond switching and femtojoule writes through ultrafast sublattice dynamics. We present the first end-to-end AFMTJ simulatio…
Spiking Neural Network Architecture Search: A Survey
Kama Svoboda, Tosiron Adegbija
This survey paper presents a comprehensive examination of Spiking Neural Network (SNN) architecture search (SNNaS) from a unique hardware/software co-design perspective. SNNs, insp…
Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture
Ilkin Aliyev, Jesus Lopez, Tosiron Adegbija
Spiking Neural Networks (SNNs) offer potential advantages in energy efficiency but currently trail Artificial Neural Networks (ANNs) in versatility, largely due to challenges in ef…
System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
Yuchao Liao, Tosiron Adegbija, Roman Lysecky
Many modern embedded systems have end-to-end (EtoE) latency constraints that necessitate precise timing to ensure high reliability and functional correctness. The combination of Hi…
Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview
Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija +1
Spiking Neural Networks (SNNs) are inspired by the sparse and event-driven nature of biological neural processing, and offer the potential for ultra-low-power artificial intelligen…
Are LLMs Any Good for High-Level Synthesis?
Yuchao Liao, Tosiron Adegbija, Roman Lysecky
The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potentia…
STT-RAM-based Hierarchical In-Memory Computing
Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija
In-memory computing promises to overcome the von Neumann bottleneck in computer systems by performing computations directly within the memory. Previous research has suggested using…
CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing
Dhruv Gajaria, Tosiron Adegbija, Kevin Gomez
Processing-in-cache (PiC) and Processing-in-memory (PiM) architectures, especially those utilizing bit-line computing, offer promising solutions to mitigate data movement bottlenec…
ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors
Dhruv Gajaria, Tosiron Adegbija
Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM's write energy and latency overheads. Given a relaxed retentio…
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning
Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija
Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. Howeve…
Deep Inverse Design for High-Level Synthesis
Ping Chang, Tosiron Adegbija, Yuchao Liao +3
High-level synthesis (HLS) has significantly advanced the automation of digital circuits design, yet the need for expertise and time in pragma tuning remains challenging. Existing…
A high-level synthesis approach for precisely-timed, energy-efficient embedded systems
Yuchao Liao, Tosiron Adegbija, Roman Lysecky
Embedded systems continue to rapidly proliferate in diverse fields, including medical devices, autonomous vehicles, and more generally, the Internet of Things (IoT). Many embedded…
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
Yuchao Liao, Tosiron Adegbija, Roman Lysecky +1
High-Level Synthesis (HLS) Design Space Exploration (DSE) is a widely accepted approach for efficiently exploring Pareto-optimal and optimal hardware solutions during the HLS proce…
Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks
Ilkin Aliyev, Tosiron Adegbija
The highly sparse activations in Spiking Neural Networks (SNNs) can provide tremendous energy efficiency benefits when carefully exploited in hardware. The behavior of sparsity in…
PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine
Ilkin Aliyev, Tosiron Adegbija
Spiking Neural Networks (SNNs) have become popular for their more bio-realistic behavior than Artificial Neural Networks (ANNs). However, effectively leveraging the intrinsic, unst…
Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators
Ilkin Aliyev. Kama Svoboda, Tosiron Adegbija
Spiking Neural Networks (SNNs) offer a promising alternative to Artificial Neural Networks (ANNs) for deep learning applications, particularly in resource-constrained systems. This…
jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research
Tosiron Adegbija
This paper introduces the jazznet Dataset, a dataset of fundamental jazz piano music patterns for developing machine learning (ML) algorithms in music information retrieval (MIR).…
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches
Kyle Kuan, Tosiron Adegbija
Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAM in on-chip caches due to several advantages. These advantages include non-volatility, low leakage, high integra…
Energy and Performance Analysis of STTRAM Caches for Mobile Applications
Kyle Kuan, Tosiron Adegbija
Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobil…
A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior
Keeley Criswell, Tosiron Adegbija
Adaptable computing is an increasingly important paradigm that specializes system resources to variable application requirements, environmental conditions, or user requirements. Ad…
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems
Kyle Kuan, Tosiron Adegbija
Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, an…