150 citations · 150 across the 1 of their papers we have counts for
2 papers
cs.AR2017★ 150 cited
Improving DRAM Performance by Parallelizing Refreshes with Accesses
Kevin K. Chang, Donghyuk Lee, Zeshan Chishti +4
Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR DRAM refreshes cells at the rank level. This degrades performance significantly beca…
cs.DC2016
RowHammer: Reliability Analysis and Security Implications
Yoongu Kim, Ross Daly, Jeremie Kim +6
As process technology scales down to smaller dimensions, DRAM chips become more vulnerable to disturbance, a phenomenon in which different DRAM cells interfere with each other's op…