269 citations · 1.1k across the 40 of their papers we have counts for
22 papers · 1 filter
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Nika Mansouri Ghiasi, Mohammad Sadrosadati, Geraldo F. Oliveira +9
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between la…
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-Efficient Genome Analysis
Can Firtina, Kamlesh Pillai, Gurpreet S. Kalsi +10
Profile hidden Markov models (pHMMs) are widely employed in various bioinformatics applications to identify similarities between biological sequences, such as DNA or protein sequen…
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices
A. Giray Yağlıkçı, Haocong Luo, Geraldo F. de Oliviera +7
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging a DRAM row, and thus alternating the voltage of a row's wordline between low and high v…
SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping
Damla Senol Cali, Konstantinos Kanellopoulos, Joel Lindegger +15
A critical step of genome sequence analysis is the mapping of sequenced DNA fragments (i.e., reads) collected from an individual to a known linear reference genome sequence (i.e.,…
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications
Jawad Haj Yahya, Haris Volos, Davide B. Bartolini +9
User-facing applications running in modern datacenters exhibit irregular request patterns and are implemented using a multitude of services with tight latency requirements. These c…
GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis
Nika Mansouri Ghiasi, Jisung Park, Harun Mustafa +11
Read mapping is a fundamental, yet computationally-expensive step in many genomics applications. It is used to identify potential matches and differences between fragments (called…
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
F. Nisa Bostancı, Ataberk Olgun, Lois Orosa +5
Random number generation is an important task in a wide variety of critical applications including cryptographic algorithms, scientific simulations, and industrial testing tools. T…
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
Jawad Haj Yahya, Jeremie S. Kim, A. Giray Yaglikci +4
To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gate…
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins
Jeremie S. Kim
This dissertation rigorously characterizes many modern commodity DRAM devices and shows that by exploiting DRAM access timing margins within manufacturer-recommended DRAM timing sp…
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati +10
DRAM is the dominant main memory technology used in modern computing systems. Computing systems implement a memory controller that interfaces with DRAM via DRAM commands. DRAM exec…
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
Ataberk Olgun, Minesh Patel, A. Giray Yağlıkçı +6
True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic pri…
pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
João Dinis Ferreira, Gabriel Falcao, Juan Gómez-Luna +8
Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottlenec…
BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display
Jawad Haj-Yahya, Jisung Park, Rahul Bera +5
Conventional planar video streaming is the most popular application in mobile systems and the rapid growth of 360 video content and virtual reality (VR) devices are accelerating th…
Accelerating Genome Analysis: A Primer on an Ongoing Journey
Mohammed Alser, Zülal Bingöl, Damla Senol Cali +4
Genome analysis fundamentally starts with a process known as read mapping, where sequenced fragments of an organism's genome are compared against a reference genome. Read mapping i…
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
Jawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim +5
Modern client processors typically use one of three commonly-used power delivery network (PDN): 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), an…
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
Yaohua Wang, Lois Orosa, Xiangjun Peng +8
DRAM Main memory is a performance bottleneck for many applications due to the high access latency. In-DRAM caches work to mitigate this latency by augmenting regular-latency DRAM w…
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics
Minesh Patel, Jeremie S. Kim, Taha Shahroodi +2
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die error-correction coding (ECC), which operates entirely within a DRAM chip to improve factory…
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl +13
Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. U…
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci +4
In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chi…
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors
Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim +4
There are three domains in a modern thermally-constrained mobile system-on-chip (SoC): compute, IO, and memory. We observe that a modern SoC typically allocates a fixed power budge…
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
Jeremie S. Kim, Minesh Patel, Hasan Hassan +2
We propose a new DRAM-based true random number generator (TRNG) that leverages DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access timing para…
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM
Vivek Seshadri, Donghyuk Lee, Thomas Mullins +7
Bitwise operations are an important component of modern day programming. Many widely-used data structures (e.g., bitmap indices in databases) rely on fast bitwise operations on lar…