3 papers
cs.AR2025
Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
He Jiang, Yi Guo, Shikai Guo +4
Timing optimization during global placement is critical for achieving optimal circuit performance and remains a key challenge in modern Field Programmable Gate Array (FPGA) design.…
cs.AI2025
Modeling Relational Logic Circuits for And-Inverter Graph Convolutional Network
Weihao Sun, Shikai Guo, Siwen Wang +2
The automation of logic circuit design enhances chip performance, energy efficiency, and reliability, and is widely applied in the field of Electronic Design Automation (EDA).And-I…
cs.LG2025
FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks
Qiyun Zhao
As integrated circuit scale grows and design complexity rises, effective circuit representation helps support logic synthesis, formal verification, and other automated processes in…