150 citations · 150 across the 1 of their papers we have counts for
9 papers
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim +2
This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significa…
RowClone: Accelerating Data Movement and Initialization Using DRAM
Vivek Seshadri, Yoongu Kim, Chris Fallin +8
In existing systems, to perform any bulk data movement operation (copy or initialization), the data has to first be read into the on-chip processor, all the way into the L1 cache,…
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechani…
Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
Yoongu Kim, Vivek Seshadri, Donghyuk Lee +2
This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was published in ISCA 2012, and examines the work's significance and future potential. Modern DRA…
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism
K. K. Chang, D. Lee, Z. Chishti +4
This article summarizes the idea of "refresh-access parallelism," which was published in HPCA 2014, and examines the work's significance and future potential. The overarching objec…