5 papers
TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
Bardia Nadimi, Khashayar Filom, Deming Chen +1
With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification…
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Designing Verilog modules requires meticulous attention to correctness, efficiency, and adherence to design specifications. However, manually writing Verilog code remains a complex…
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Bardia Nadimi, Ghali Omar Boutaib, Hao Zheng
Recently, there has been a growing interest in leveraging Large Language Models for Verilog code generation. However, the current quality of the generated Verilog code remains subo…
Modulo- Arithmetic via Two Parallel n-bit Residue Channels
Ghassem Jaberipur, Bardia Nadimi, Jeong-A Lee
Augmenting the balanced residue number system moduli-set , with the co-prime modulo , increases the dynamic range (DR) by around 70%.…
Forward and Reverse Converters for the Moduli-Set
Ghassem Jaberipur, Bardia Nadimi, R. Kazemi +1
Modulo- adders have recently been implemented using the regular parallel prefix (RPP) architecture, matching the speed of the widely used modulo-$(2^q \pm 1)…